1. Field of the Invention
The present invention relates generally to a semiconductor memory device and a method of manufacturing the same. More particularly, the invention relates to a semiconductor memory device having a fin transistor and a planar transistor and a method of manufacturing the same.
A claim of priority is made to Korean Patent Application No. 10-2004-0083691 filed on Oct. 19, 2004, the disclosure of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
Field effect transistors (FETs) are perhaps the most common elements found in modern semiconductor integrated circuits (ICs). Within contemporary semiconductor ICs, FETs are characterized by decreasing size and, therefore, increasing fabrication density. This trend is important because significant performance gains in semiconductor ICs may be obtained by producing smaller, more densely packed (i.e., more highly integrated) FETs.
Unfortunately, the fabrication of smaller, more densely packed FETs can lead to a variety of operational and structural problems. For example, scaling down the size of a FET can lead to a phenomenon called “punch through”, whereby source and drain depletion regions fuse together to form a single depletion region, thereby causing drain current to become highly dependent on a drain-source voltage.
Fin FET transistors have been introduced to address the punch through problem, among other problems. A fin FET transistor (hereafter, “fin transistor”) includes a silicon fin structure formed on a semiconductor substrate and a gate electrode formed across the fin structure. The gate electrode is formed in contact with an upper surface and sidewalls of the fin structure. A channel region under the gate electrode is defined by the upper surface and sidewalls of the fin structure. As such, the fin structure effectively creates a wide channel within a limited space, thus allowing a significant amount of current to flow through the channel when the transistor is turned on. In addition, since the gate electrode controls the channel region through the upper surface and sidewalls thereof, the gate is able to more effectively control the channel region to prevent undesirable effects such as punch-through. Because of the above-described characteristics, the fin transistor can be applied to various semiconductor devices.
Semiconductor devices may include fin transistors together with planar FETs (hereafter, planar transistors). A planar transistor is a conventional transistor with a planar channel region. In certain semiconductor devices, in particular, dynamic random access memory (DRAM) devices, the fin transistor may be formed in a cell region, and the planar transistor may be formed in a peripheral circuit region next to the cell region.
FIGS. 1 through 3 are perspective views illustrating a method of forming a semiconductor device having a conventional fin transistor and a planar transistor. In FIGS. 1 through 3, reference symbol “a” indicates a fin region where a fin transistor is formed, and reference symbol “b” indicates a planar region where a planar transistor is formed.
Referring to FIG. 1, first and second hard mask patterns 3a and 3b are formed on a semiconductor substrate 1 in respective regions “a” and “b”. Semiconductor substrate 1 is anisotropically etched using first and second hard mask patterns 3a and 3b as an etch mask to form a fin active region 5a in fin region “a” and a planar active region 5b in planar region “b”. Planar active region 5b is formed to be wider than fin active region 5a, and upper surfaces of fin and planar active regions 5a and 5b have roughly the same height.
Fin active region 5a and planar active region 5b are bounded by respective first and second trenches formed by the anisotropic etching. After fin and planar active regions 5a and 5b are formed, a silicon oxide layer 7 filling the first and second trenches is formed on a whole surface of semiconductor substrate 1.
Referring to FIG. 2, a preliminary fin device isolation layer 7a and a planar device isolation layer 7b are formed in respective fin and planar regions “a” and “b” by planarizing silicon oxide layer 7 until hard mask patterns 3a and 3b are exposed. A photo sensitive pattern (not shown) covering planar region “b” is then formed. The preliminary fin device isolation layer is etched to form a fin device isolation layer 7a covering lower sidewalls of fin active region 5a . Thus, upper sidewalls of fin active region 5a are left exposed. Fin device isolation layer 7a has a relatively low height compared with planar device isolation layer 7b . Hard mask patterns 3a and 3b are selectively removed to expose upper surfaces of fin and planar active regions 5a and 5b. 
A thermal oxidation process is performed on semiconductor substrate 1 to form a sidewall gate oxide layer 9a on exposed areas of fin active region 5a and a planar gate oxide layer 9b on exposed areas of planar active region 5b. A gate conductive layer 11 is then formed over an entire surface of the semiconductor substrate 1.
Referring to FIG. 3, gate conductive layer 11 is patterned to form a fin gate electrode 11a crossing fin active region 5a and a planar gate electrode 11b crossing planar active region 5b. Fin gate electrode 11a is formed in contact with an upper surface and both sidewalls of fin active region 5a, and planar gate electrode 11b is in contact with an upper surface of planar active region 5b. 
In the above-described method, gate conductive layer 11 is formed with different thicknesses on fin and planar regions “a” and “b” owing to the difference in the heights of respective fin and planar device isolation layers 7a and 7b. Accordingly, gate electrodes 11a and 11b have different heights and therefore a greater portion of gate conductive layer 11 has to be etched to form gate electrode 11a than to form gate electrode 11b. 
Because a greater portion of gate conductive layer 11 must be etched to form gate electrode 11a, planar gate oxide layer 9b and planar active region 5b on both sides of planar gate electrode 11b may be excessively etched while gate electrode 11a is being formed. As a result, planar gate oxide layer 9b and planar active region 5b may be damaged. This damage often results in defects to the electrical characteristics of the fin transistor. For example, leakage current may flow through source/drain regions (not shown) at both sides of planar gate electrode 11b, and a contact resistance therebetween may be increased.